The present invention relates to a video intermediate frequency processing apparatus which performs video detection in a television receiver.
In general, a television signal is tuned to a desired channel by a tuner which functions as a television receiver, and thereafter, is converted into a video intermediate frequency signal on the basis of an oscillation frequency of a local oscillator circuit so that a prescribed video intermediate frequency f0 (e.g., in Japan, f0=58.75 MHz, and in U.S., f0=45.75 MHz) is transmitted as a carrier wave. So, in the television receiver, an AFT (Automatic Frequency Tuning) circuit detects a shift between a carrier frequency of a video intermediate frequency outputted from a tuner and the video intermediate frequency f0 so that an oscillation frequency obtained by the local oscillator circuit becomes a true video intermediate frequency, and then, feeds the detection result back to the local oscillator circuit of the tuner. In the manner as described above, a frequency of the video intermediate signal outputted from the tuner is coincident with a video intermediate frequency.
The tuner can stably output a video intermediate signal using this feedback control, and then, the outputted video intermediate signal is inputted to a next-stage video intermediate frequency processing apparatus. The video intermediate frequency processing apparatus is an apparatus for video detection with respect to the inputted video intermediate signal. In general, the video intermediate frequency processing apparatus includes various circuits such as an AFT circuit for carrying out the above feedback control.
The following is a description a construction and operation of a conventional video intermediate frequency processing apparatus. FIG. 3 is a block diagram schematically showing a construction of a conventional video intermediate frequency processing apparatus 300. In general, the video intermediate frequency processing apparatus is realized by an IC (Integrated Circuit), and employs a video detection system using a PLL (Phase-Locked Loop). In order to simplify the explanation, parts of the IC having no relation with the present invention are omitted from the figure.
The conventional video intermediate frequency processing apparatus 300 receives a video intermediate signal (VIF signal) in a VIF-AMP 11 such as an AGC (Auto Gain Control) amplifier via a pad P1. In this case, the inputted video intermediate signal is outputted from a tuner (not shown), and thereafter, is inputted to an intermediate frequency filter (not shown) such as a SAW (Surface Acoustic Wave) filter or the like, and thereby, becomes a signal which is in a state of removing unnecessary signals of adjacent channels.
A signal passing through the VIF-AMP 11 is inputted to a video signal detection circuit (VIDEO-DET.) 12, and then, a video AM detection is made herein. Then, a video detection signal (VIDEO detection output), which is the detection result of the VIDEO-DET. 12, is outputted via a pad P4, and thus, is inputted to an IF-AGC circuit 13.
The IF-AGC circuit 13 is a circuit for detecting a synchronizing amplitude, and operating the VIF-AMP 11 so that a video detection signal always has a constant level. More specifically, the VIF-AMP 11 receives the detection result of the IF-AGC circuit 13 as an AGC voltage, and thereby, even if an amplitude of a VIF signal inputted to the video intermediate frequency processing apparatus changes, it is possible to make the signal constant after video AM detection. In this case, a signal outputted from the IF-AGC circuit 13 is connected to an IF-AGC filter 14, which functions as a low-pass filter, via a pad P2, and is integrated to a sufficient DC (direct current) voltage as an AGC voltage of the VIF-AMP 11.
Moreover, as shown in FIG. 3, a PLL is composed of a phase detector (APC) 15, a voltage control oscillator (VCO) 16, and an APC filter 17 which is connected via a pad P3 and functions as a low-pass filter, and generates a signal having the same frequency and phase as a carrier-wave of the VIF signal. The above VIDEO-DET. 12 receives a signal generated by the PLL, that is, an output signal from the VCO 16 for synchronous detection, and thus, can output a base-band video detection signal which is a detection output.
The output signal of the VCO 16 constituting the above PLL is also inputted to an AFT circuit 18. As described before, the AFT circuit 18 is a circuit which detects a shift between a carrier frequency of the VIF signal and the video intermediate frequency f0, and outputs a DC voltage in accordance with the shift. The function and operation of the AFT circuit itself have been generally widely known; therefore, the details are omitted.
In this case, as the AFT circuit 18, it is preferable to use the prior invention xe2x80x9cAFT circuitxe2x80x9d made by the same invention who made the present invention. The prior invention xe2x80x9cAFT circuitxe2x80x9d compares an output signal frequency of the above VCO 16 with a reference signal frequency produces by a stable oscillator, such as a crystal oscillator circuit or the like, and thereby, realizes stable AFT operation without depending upon dispersion factors such as an offset of component circuit and temperature characteristic.
For example, when the output signal frequency of the VCO 16 is equal to the video intermediate frequency f0, the aforesaid AFT circuit 18 outputs a voltage Vcc/2 (Vcc: supply voltage) On the other hand, when the output signal frequency of the VCO 16 is lower than the video intermediate frequency f0, the aforesaid AFT circuit 18 outputs a DC voltage higher than Vcc/2; conversely, when the output signal frequency of the VCO 16 is higher than the video intermediate frequency f0, the aforesaid AFT circuit 18 outputs a DC voltage lower than Vcc/2, in accordance with a shift of frequency.
The DC voltage outputted from the AFT circuit 18 is inputted to an AFT-DEFEAT circuit 19. The AFT-DEFEAT circuit 19 is a circuit for preventing a malfunction of the AFT circuit 18, and makes a decision whether or not a DC voltage outputted from the AFT circuit 18 should be outputted as an AFT voltage via a pad P5. In this case, the IF-AGC circuit 13 can detect a weak electric field state and a no-signal state of the video detection signal. Moreover, a lock detector (LOCK-DET.) 20 shown in FIG. 3 is a circuit which receives a video detection signal of being the detection result of the VIDEO-DET. 12, and detects a state that the PLL is unlocked.
The AFT-DEFEAT circuit 19 inputs the detection result outputted from the IF-AGC circuit 13 and LOCK-DET. circuit 20, and then, in the case where the input detection result shows a weak electric field state, no signal state or a state that the above PLL is unlocked, fixedly outputs xc2xd Vcc as an AFT voltage without outputting the DC voltage outputted from the AFT circuit 18 as the AFT voltage.
The video intermediate frequency processing apparatus has the circuit configuration as described above, and thereby, realizes a video detection and a stable video intermediate signal output from a tuner. However, a free-running frequency of the VCO 16 has a dispersion to some degree in an IC manufacturing process; for this reason, the free-running frequency needs to be adjusted so as to become the same as the video intermediate frequency f0. In particular, the adjustment must be accurately made in order to secure a pull-in frequency range of the PLL and to prevent a characteristic deterioration of video detection output due to a static phase error.
Usually, the adjustment of the free-running frequency is made in the following manner. More specifically, first, a VIF signal is put in a no-signal state, and as shown in FIG. 3, a switch SW 10 for grounding the pad P2 connected to the IF-AGC filter 14 is turned on, thereby, making minimum a gain of the VIF-AMP 11, that is, a state having no influence from a disturbance. In this state, a free-running frequency control voltage inputted to the VCO 16 is changed while measuring a signal component frequency of the VCO 16 slightly leaking from the pad P4, and thus, the adjustment of frequency is made.
However, according to the aforesaid free-running frequency adjusting method, in order to measure the frequency, an expensive measuring instrument such as a spectrum analyzer must be connected to the pad P4. For this reason, in a TV set manufacture line, there is a problem that it is difficult to make an adjustment of free-running frequency. In this case, as means for supplying a free-running frequency control voltage, in recent years, there are many cases where of converting an adjustment signal from an external microcomputer into a DC signal using A/D converter used in a bus/interface circuit in the IC, and thereafter, supplying the adjustment signal.
It is an object of the present invention to provide a video intermediate frequency processing apparatus which can readily adjust a free-running frequency of a VCO constituting a PLL.
In order to solve the above problem and to achieve the above object, the video intermediate frequency processing apparatus according to one aspect of the present invention comprises an amplifying unit for amplifying a video intermediate signal outputted from a tuner, and for making minimum its gain in accordance with an input of invalid signal; a phase locked loop unit including; a voltage control oscillator circuit which outputs an output signal having an oscillation frequency in accordance with a control voltage and changes a free-running frequency in accordance with a free-running frequency adjustment voltage; and a phase detector circuit which makes a phase detection between the video intermediate signal amplified by the amplifying unit and the output signal, and inputting a signal obtained on the basis of the phase detection result of the phase detector circuit to the voltage control oscillator circuit as the control voltage; a video signal detecting unit for making a video detection with respect to the video intermediate signal amplified by the amplifying unit using the output signal so as to output a video detection signal; an automatic frequency tuning unit for converting a frequency change of the output signal into a direct current voltage, and for outputting the direct current voltage as a temporary voltage for a feedback input to the tuner so that a frequency of the video intermediate signal becomes a predetermined video intermediate frequency; a video detection signal detecting unit for detecting a weak electric field state or no signal state of the video detection signal so as to output an abnormal signal; an automatic frequency tuning voltage generating unit for generating and outputting an automatic frequency tuning voltage fed back and inputted to the tuner on the basis of the temporary voltage, while outputting a predetermined automatic frequency tuning voltage when the abnormal signal is inputted; and a switching unit for preventing the abnormal signal from being inputted to the automatic frequency tuning voltage generating unit in accordance with the invalid signal.
According to the present invention, in the case of adjusting a free-running frequency of a voltage control oscillator circuit, an invalid signal (equivalent to a VIF-DEFEAT signal which will be described later) is inputted to an amplifier unit so as to make minimum a gain of the amplifier unit, and thereby, it is possible to fully set the voltage control oscillator circuit to a free-running state. Moreover, at that time, a switching unit is made into an off state by the invalid signal, and thereby, the detection result (abnormal signal) of a video detection signal detecting unit is prevented from being inputted to an automatic frequency tuning voltage generating unit. Therefore, it is possible to obtain a direct voltage indicative of a difference between a free-running frequency and a video intermediate frequency from the automatic frequency tuning voltage generating unit.
The video intermediate frequency processing apparatus according to one aspect of the present invention comprises an amplifying unit for amplifying a video intermediate signal outputted from a tuner, and for making minimum its gain in accordance with an input of invalid signal; a phase locked loop unit including; a voltage control oscillator circuit which outputs an output signal having an oscillation frequency in accordance with a control voltage and changes a free-running frequency in accordance with a free-running frequency adjustment voltage; and a phase detector circuit which makes a phase detection between the video intermediate signal amplified by the amplifying unit and the output signal, and inputting a signal obtained on the basis of the phase detection result of the phase detector circuit to the voltage control oscillator circuit as the control voltage; a video signal detecting unit for making a video detection with respect to the video intermediate signal amplified by the amplifying unit using the output signal so as to output a video detection signal; an automatic frequency tuning unit for converting a frequency change of the output signal into a direct current voltage, and for outputting the direct current voltage as a temporary voltage for a feedback input to the tuner so that a frequency of the video intermediate signal becomes a predetermined video intermediate frequency; a video detection signal detecting unit for detecting a weak electric field state or no signal state of the video detection signal so as to output an abnormal signal; an automatic frequency tuning voltage generating unit for generating and outputting an automatic frequency tuning voltage fed back and inputted to the tuner on the basis of the temporary voltage, while outputting a predetermined automatic frequency tuning voltage when the abnormal signal is inputted; a first switching unit for preventing the abnormal signal from being inputted to the automatic frequency tuning voltage generating unit in accordance with the invalid signal; and a second switching unit for preventing the control voltage from being inputted to the voltage control oscillator circuit in accordance with the invalid signal.
According to the present invention, in the case of adjusting a free-running frequency of a voltage control oscillator circuit, an invalid signal (equivalent to an SW control signal which will be described later) is inputted to a second switching unit, and thereby, no control voltage is inputted to the voltage control oscillator circuit; therefore, it is possible to fully set the voltage control oscillator circuit to a free-running state. Moreover, at that time, a first switching unit is made into an off state by the invalid signal, and thereby, the detection result (abnormal signal) of a video detection signal detecting unit is prevented from being inputted to an automatic frequency tuning voltage generating unit. Therefore, it is possible to obtain a direct voltage indicative of a difference between a free-running frequency and a video intermediate frequency from the automatic frequency tuning voltage generating unit.
Further, a change of the free-running frequency is obtained as a change of the direct current voltage, and the invalid signal is inputted via the bus. Therefore, it is possible to read the direct current voltage outputted from the automatic frequency tuning voltage generating unit by a microcomputer, and to easily make an automatic adjustment of the free-running frequency.
Further, the free-running frequency adjustment voltage is selected as a fixed bias value by a zapping unit, and thereby, a wafer stage of chip before mold sealing, an adjustment of free-running frequency according to the present invention is carried out, and then, the free-running frequency is trimmed to some degree.
Further, the voltage control oscillator circuit can be provided with an ordinary metal fuse or Zener diode as the zapping unit; therefore, it is possible to readily perform zapping.